1. Technical Field
The present invention relates to a test apparatus and a selection apparatus. More particularly, the present invention relates to a test apparatus for testing a memory under test including therein repairing columns that are provided so as to collectively replace columns, and to a selection apparatus for use in the test apparatus.
2. Related Art
A flash memory is known as a nonvolatile semiconductor memory. The flash memory is widely used in various types of information devices and the like. A typical memory device including therein a flash memory has an enormous number of storage cells, and the storage cells may contain some defective storage cells. In view of this, the memory device includes therein redundant storage cells which can replace the defective storage cells during a test process of the memory device. By replacing the defective storage cells with the redundant storage cells, the defective storage regions of the memory devices are saved. The operation of replacing the defective storage cells with the redundant storage cells is generally performed during the test process of the memory device, and is referred to as a memory repairing operation (or redundancy).
To perform the memory repairing operation, it is required to detect the positions of the defective storage cells and to conduct an analysis in order to determine in advance how to replace the detected defective storage cells with the redundant storage cells. This procedure is referred to as a memory repairing analysis and performed by a test apparatus.
Since no prior art documents have been found, such documents are not mentioned herein.
The test apparatus performs the memory repairing analysis in the following manner, for example. The test apparatus conducts a test on the memory under test to obtain failure information, and writes the obtained failure information into a failure memory. Subsequently, the test apparatus reads the failure information from the failure memory, and counts the number of errors. Since the test apparatus performs the memory repairing analysis by writing and reading the failure information as mentioned above, the memory repairing analysis is time consuming.
Here, the test apparatus can not perform different operations while performing the memory repairing analysis. Therefore, the time required for the memory repairing analysis is a dead time during the test process. Note that the capacity of the flash memory has been on the rise recently, and the test time is thus expected to increase. For the reasons stated above, it is desired to reduce the time necessary for the memory repairing analysis.
This need may be satisfied by a method which temporarily stores, on the failure memory, the failure information which has not been compressed and compresses the failure information in terms of the software. However, this method does not solve the problem that a long time is required to read the failure information.